1. Field of the Invention
This invention relates to a timing recovering apparatus for recovering timing of received data signal and to an automatic slice apparatus for detecting the data signal by comparing the data signal with a reference level controlled, and particularly relates to a timing recovering apparatus used in a digital magnetic reproducing apparatus for reproducing a video signal or a sound signal and to an automatic slice apparatus used in a digital magnetic reproducing apparatus for reproducing a video signal or a sound signal.
2. Description of the Prior Art
A timing recovering apparatus for recovering timing of received data signal used in a digital magnetic reproducing apparatus for reproducing a video signal or a sound signal after a/d conversion is known. Such timing recovering apparatus is used for recovering timing of interleaved NRZI (I-NRZI) coded digital data signal. In the timing recovering apparatus, the reproduced or transmitted interleaved NRZI coded digital data signal is supplied to an equalizer circuit for frequency-compensating to produce a data signal having partial response waveform, hereinafter referred to as PR (1, 0,-1). The equalized data signal shows a three-valued eye pattern, that is, it shows three levels (1, 0, and -1), that is, it is represented by three-valued notation. The equalized data signal is compared with two different reference levels by comparators. A logic circuit detects change in logic level of outputs of the comparators and a clock generation circuit produces a reproduced clock signal with timing of the receive data signal recovered.
An automatic slice apparatus for detecting the data signal by comparing the data signal with reference levels controlled in accordance with a magnitude of the output of the equalizer is known. It is used in a digital magnetic recording apparatus and a digital magnetic reproducing apparatus. Such automatic slice apparatus detects the received digital data signal by comparing such that the reference level is controlled to the center level of the eye pattern of the received data signal to effect accurate comparison. Such comparison reduces fluctuation in amplitude of received digital data signal. Such fluctuation may be developed at a magnetic head for reading a recorded data signal. Such automatic slice apparatus can used together with the timing recovering circuit mentioned above. In this case, the automatic slice circuit generates two different reference levels for comparing the equalized data signal having partial response waveform.
FIG. 6 is a block diagram of a prior art timing recovering apparatus having a prior art automatic slice circuit. FIGS. 7A to 7F show waveforms for explaining a prior art timing recovering apparatus.
A digital data signal reproduced from a magnetic recording medium 31 by a magnetic head 32 is applied to an equalizing circuit 33 for frequency-compensating the received data signal to produce a data signal having partial response (PR) waveform. The equalized data signal shows three-valued eye pattern. The equalized data signal is compared by comparing circuits 34 and 35. Comparing circuits 34 and 35 have different reference levels C1 and C2 shown in FIG. 7A to discriminate the equalized data signal into three level ranges with their binary outputs. The comparing circuit 35 having the reference level C2 outputs an inverted output such that a level of -1 is outputted as 1. The binary outputs from the comparator 34 and 35 are inputted to an Exclusive OR circuit 36 for effecting Exclusive OR operation.
A clock signal generation circuit 37 for detecting bit phase, comprises a tank circuit 38, multiplier 39, low-pass filter (LPF) 40, and a voltage controlled oscillator (VCO) 41. In response to edge portions of the binary output of the Exclusive OR 36, the tank circuit 38 generates a clock signal whose frequency corresponds to the reproduced clock signal of the timing recovering circuit. The output signal of the tank circuit 38 is applied to a phase locked loop (PLL) circuit including the multiplier 39, low-pass filter 40 and the voltage controlled oscillator 41. Therefore, the phase locked loop circuit outputs the clock signal with timing recovered from the received digital data signal.
In this prior art timing recovering circuit, a phase of the output of the tank circuit 38 may change in accordance with pattern of data. FIG. 7A shows eye pattern of the output of the equalizer 36, the eye pattern being to be discriminated into three values. In FIG. 7A, the output of the equalizer 36 is normally discriminated at timings A0, B0, C0, and D0 with the same possibility substantially, so that the the tank circuit 38 generates a sine signal as shown in FIG. 7B with phases of respective waves of the sine signal (.omega..sub.o t) averaged.
However, when the data signal indicative of a specific data pattern, that is, a waveform W1 represented by (1, 0, -1, 0, 1) of three-valued notation, is inputted repeatedly to the prior art timing recovering circuit, the output of the Exclusive OR circuit 36 outputs a signal shown in FIG. 7E because the output of the comparing circuit 34 shows a waveform shown in FIG. 7C and the output of the comparing circuit 35 shows a waveform shown in FIG. 7D.
Accordingly, the tank circuit 38 would output a signal represented by waveform W5 in response to falling edges of the output of the Exclusive OR circuit 36. On the other hand, the tank circuit 38 would output a signal represented by waveform W6 in response to rising edges of the output of the Exclusive OR circuit 36. In fact, due to averaging, the tank circuit 38 outputs a signal represented by a waveform W4, that is, a signal of sin (.omega..sub.o t+.pi./2). This signal represented by the waveform W4 is different in phase by .pi./2 from the waveform shown in FIG. 7B, so that bit slip occurs. That is, bias of data pattern causes phase shift of the reproduced clock signal, so that there is a problem that bit synchronizing cannot be obtained accurately by this prior art timing recovering circuit.
In FIG. 6, an automatic slice circuit 42 controls a reference level for the comparing circuits 34 and 35 in accordance with a detected amplitude of the output of the equalizer 33. The output of the equalizer 33 is applied to a squaring circuit 43 for detecting an absolute amplitude of the output of the equalizer 33 which is sent to a low-pass filter 44 for removing high frequency component to produce the reference level. The reference level is sent to a reference signal generation circuit 28 for generating the reference levels C1 and C2 for the comparing circuits 34 and 35. Comparing circuits 34 and 35 discriminate the received data signal into three-valued notation from the reference level.
This automatic slice circuit 42 causes the comparing circuits 34 and 35 to discriminating the received data signal into three-valued notation with variation in amplitude of the output of the equalizer 33 caused by the magnetic head 32.
However, because the pass band of the received data signal is limited to obtain partial response (1, 0, -1) in this system, bias of data pattern causes variation in amplitude at the output of the equalizer 33. For example, a data pattern represented by a waveform W2 indicated by three-value notation (1, 1, -1, -1) shown in FIG. 7A shows such variation.
Therefore, there is a problem that the reference level for comparing is inaccurate due to bias of data pattern of the received data signal in this prior art automatic slice circuit 42. Moreover, there is a further problem that such prior art automatic slice circuit 42 is adversely affected by external noises because such prior art automatic slice circuit has an open-loop structure, or feedforward structure.